A high speed and low power CMOS/SOS multiplier-accumulator
- 1 November 1983
- journal article
- Published by Elsevier in Microelectronics Journal
- Vol. 14 (6), 49-57
- https://doi.org/10.1016/s0026-2692(83)80084-6
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistorIEEE Transactions on Electron Devices, 1980
- A Proof of the Modified Booth's Algorithm for MultiplicationIEEE Transactions on Computers, 1975
- A Suggestion for a Fast MultiplierIEEE Transactions on Electronic Computers, 1964