Measurement of interface trap states in metal–ferroelectric–silicon heterostructures

Abstract

Interface trap density distributions within Si for metal–bismuth titanate–silicon capacitors fabricated by chemical solution deposition were investigated. The interface trap density was measured by a conductance technique at room temperature and a value in the order of ${10}^{11}{\text{–10}}^{12}\hspace{0.17em}{\mathrm{eV}}^{\mathrm{-1}}{\mathrm{\hspace{0.17em}cm}}^{\mathrm{-2}}$ was found depending on the ferroelectric crystallization temperature. An increase in the annealing temperature results in an increase in the interface trap density.