Retiming and resynthesis: optimizing sequential networks with combinational techniques
- 4 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. i, 397-406
- https://doi.org/10.1109/hicss.1990.205140
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- Approaches to multi-level sequential logic synthesisPublished by Association for Computing Machinery (ACM) ,1989
- Decomposition and factorization of sequential finite state machinesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Logic Minimization Algorithms for VLSI SynthesisPublished by Springer Nature ,1984
- Optimizing Synchronous Circuitry by Retiming (Preliminary Version)Published by Springer Nature ,1983
- Optimizing synchronous systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981