MIS: A Multiple-Level Logic Optimization System
- 1 November 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 6 (6), 1062-1081
- https://doi.org/10.1109/tcad.1987.1270347
Abstract
No abstract availableThis publication has 7 references indexed in Scilit:
- A Rule-Based System for Optimizing Combinational LogicIEEE Design & Test of Computers, 1985
- LSS: A system for production logic synthesisIBM Journal of Research and Development, 1984
- Logic Minimization Algorithms for VLSI SynthesisPublished by Springer Nature ,1984
- A High Level Synthesis Tool for MOS Chip DesignPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A VLSI RISCComputer, 1982
- Logic Synthesis Through Local TransformationsIBM Journal of Research and Development, 1981
- An Approach to Multilevel Boolean MinimizationJournal of the ACM, 1964