Atomic force microscope study of amorphous silicon and polysilicon low-pressure chemical-vapor-deposited implanted layers
- 1 January 2000
- journal article
- Published by American Vacuum Society in Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures
- Vol. 18 (1), 41-47
- https://doi.org/10.1116/1.591148
Abstract
The roughness of the poly/interpoly oxide interface plays a most important role in the performance of devices; it is expected that for a smoother interface, the double-polysilicon structure will present better electrical properties, such as higher breakdown voltage, and will be more reliable. To obtain the best electrical properties of the oxide layer, it is, therefore, essential to control the polysilicon morphological properties. The overall performances will be affected by the postdeposition process: implantation (dose, energy, and ion), oxidation (temperature, time, ambient), and preoxidation cleaning procedures. In this study, polysilicon and amorphous silicon films were produced under different controlled process conditions and were analyzed using atomic force microscopy (AFM). Significant differences in morphology between polysilicon and amorphous silicon films were obtained. Polysilicon roughness is an order of magnitude higher than amorphous silicon. Roughness of amorphous silicon films increased after rapid thermal annealing treatment performed after deposition. Phosphorus implantations at doses of and energy of 40 keV affect the grain size. Implantation doses between and and implantation energies between 40 and 100 keV do not affect the topography. The roughness of the amorphous silicon film increased as a result of the cleaning process, which involves growing an oxide layer and stripping it with hydrofluoric acid. Poor morphology information was gained from high resolution scanning electron microscopy imaging of these films. We conclude that AFM scanning can obtain quantitative and qualitative morphology information of amorphous and polysilicon layers deposited on silicon wafers.
Keywords
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