An on-chip high-voltage generator circuit for EEPROMs with a power supply voltage below 2 V

19 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 75-76
https://doi.org/10.1109/vlsic.1995.520692

Abstract

We propose an on-chip high-voltage generator circuit for low-voltage EEPROMs composed of a pMOSFET-based charge pump circuit driven by bootstrapped clock generators. The voltage gain per unit stage does not suffer from the threshold voltage drop. The device implemented in a 1.2 /spl mu/m CMOS technology operates as low as 1 V.

Keywords

POWER GENERATION
EPROM
POWER SUPPLIES
THRESHOLD VOLTAGE
CHARGE PUMPS
CLOCKS
COUPLING CIRCUITS
CMOS TECHNOLOGY
LOW VOLTAGE
PARASITIC CAPACITANCE

This publication has 2 references indexed in Scilit:

Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits
IEEE Journal of Solid-State Circuits, 1989
On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique
IEEE Journal of Solid-State Circuits, 1976

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