A true single-phase-clock dynamic CMOS circuit technique
- 1 October 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 22 (5), 899-901
- https://doi.org/10.1109/jssc.1987.1052831
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- Fully Dynamic Switch-Level Simulation of CMOS CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- A Design Style for VLSI CMOSIEEE Journal of Solid-State Circuits, 1985
- NORA: a racefree dynamic CMOS technique for pipelined logic structuresIEEE Journal of Solid-State Circuits, 1983