A Switch-Level Timing Verifier for Digital MOS VLSI
- 1 July 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 4 (3), 336-349
- https://doi.org/10.1109/tcad.1985.1270130
Abstract
No abstract availableThis publication has 9 references indexed in Scilit:
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- Architecture of a VLSI instruction cache for a RISCPublished by Association for Computing Machinery (ACM) ,1983
- A Multiple Media Delay Simulator for MOS LSI CircuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- Timing Analysis for nMOS VLSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- Signal Delay in RC Tree NetworksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981