Razor: circuit-level correction of timing errors for low-power operation
Top Cited Papers
- 1 November 2004
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro
- Vol. 24 (6), 10-20
- https://doi.org/10.1109/mm.2004.85
Abstract
Dynamic voltage scaling is one of the more effective and widely used methods for power-aware computing. We present a DVS approach that uses dynamic detection and correction of circuit timing errors to tune processor supply voltage and eliminate the need for voltage marginsKeywords
This publication has 8 references indexed in Scilit:
- Circuit-aware architectural simulationPublished by Association for Computing Machinery (ACM) ,2004
- The implementation and application of micro rollback in fault-tolerant VLSI systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Automatically characterizing large scale program behaviorPublished by Association for Computing Machinery (ACM) ,2002
- SimpleScalar: an infrastructure for computer system modelingComputer, 2002
- Closed-loop adaptive voltage scaling controller for standard-cell ASICsPublished by Association for Computing Machinery (ACM) ,2002
- Power: a first-class architectural design constraintComputer, 2001
- The simulation and evaluation of dynamic voltage scaling algorithmsPublished by Association for Computing Machinery (ACM) ,1998
- Supply and threshold voltage scaling for low power CMOSIEEE Journal of Solid-State Circuits, 1997