Analysis of noise margin and speed of GaAs MESFET DCFL using UM-SPICE

Abstract

Using a customized GaAs IC circuit simulator (UM-SPICE) the design trade-offs and process sensitivity of the logic levels, noise margin, and propagation delay for GaAs direct coupled field effect logic (DCFL) gates are analyzed. The results of the circuit simulation are shown to be in good agreement with our experimental data. For DCFL gates with ungated FET loads studied here, the noise margin is found to be the more important design criteria. The noise margin is a sensitive function of both the driver-to-load current ratio and the driver threshold voltage, whereas the propagation delay remains fairly constant over a wide range of driver-to-load ratios and threshold voltages. Our simulations indicate that a driver-to-load ratio of about 5 and a threshold voltage of about 0.1 V would offer the optimum performance for most applications. Also, the DCFL design with shallow channel transistor appears to be less sensitive to the substrate or implantation variations.