A fast, latching comparator for 12 bit A/D applications
- 1 December 1980
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 15 (6), 949-954
- https://doi.org/10.1109/JSSC.1980.1051502
Abstract
High-speed, 12 bit accurate successive approximation A/D converters demand a comparator with both excellent input specifications and fast response time. The author describes a voltage comparator with 50 ns response time to 1/2 LSB overdrive (1.2 mV) and 0.1 LSB (250 /spl mu/V) total input error. Unique features of the circuit include a super-/spl beta/ input stage, a fast buried-zener level-shift, a fully differential output stage, a floating-zener biasing scheme, and a fast latch circuit which does not interfere with input accuracy. The comparator is manufactured on a bipolar, double-implanted, thin epi, junction-isolated process.Keywords
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