Random Pattern Testability
- 1 January 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-33 (1), 79-90
- https://doi.org/10.1109/tc.1984.5009315
Abstract
A major problem in self testing with random inputs is verification of the test quality, i.e., the computation of the fault coverage. The brute-force approach of using full-fault simulation does not seem attractive because of the logic structure volume, and the CPU time encountered. A new approach is therefore necessary. This paper describes a new analytical method of computing the fault coverage that is fast compared with simulation. If the fault coverage falls below a certain threshold, it is possible to identify the ``random-pattern-resistant'' faults, modify the logic to make them easy to detect, and thus, increase the fault coverage of the random test.Keywords
This publication has 15 references indexed in Scilit:
- Testing by Verifying Walsh CoefficientsIEEE Transactions on Computers, 1983
- The Weighted Syndrome Sums Approach to VLSI TestingIEEE Transactions on Computers, 1981
- Design for Autonomous TestIEEE Transactions on Computers, 1981
- Correction to "Syndrome-Testable Design of Combinational Circuits"IEEE Transactions on Computers, 1980
- Syndrome-Testable Design of Combinational CircuitsIEEE Transactions on Computers, 1980
- Analysis of the Signal Reliability Measure and an Evaluation ProcedureIEEE Transactions on Computers, 1979
- Output probability expression for general combinational networksMicroelectronics Reliability, 1978
- Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic NetworksIEEE Transactions on Computers, 1975
- Probabilistic Treatment of General Combinational NetworksIEEE Transactions on Computers, 1975
- Analysis of Logic Circuits with Faults Using Input Signal ProbabilitiesIEEE Transactions on Computers, 1975