Interface trap profile near the band edges at the 4H-SiC/SiO2 interface

Abstract

The transconductance of SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) is typically much lower in devices fabricated on the 4H-SiC polytype compared to 6H. It is believed that this behavior is caused by extreme trapping of inversion electrons due to a higher density of traps $D_{\mathrm{it}}$ at the ${\mathrm{SiC/SiO}}_{\mathrm{2}}$ interface in 4H-SiC. Here we present an approach for profiling $D_{\mathrm{it}}$ versus energy in the band gap using a modified capacitance–voltage technique on large-area MOSFETs. We find that $D_{\mathrm{it}}$ increases towards the conduction band edge $E_c$ in both polytypes, and that $D_{\mathrm{it}}$ is much higher in 4H- compared to 6H-SiC for devices fabricated in the same process lot.