An integrated approach for hierarchical verification of VLSI mask artwork
- 1 April 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 20 (2), 501-509
- https://doi.org/10.1109/JSSC.1985.1052336
Abstract
An integrated design system (IDS) for handcrafted digital VLSI circuits is presented. Developed over a two-year period, IDS consists of both in-house and third-party software, integrated with a hierarchical top-down design methodology. A key component of IDS is the Structured LAyout VErification (SLAVE) program for electrical verification of mask artwork. Implementation of a top-down design methodology allows SLAVE to use the separate hierarchical representations in the logic, circuit, and layout models to completely verify the connectivity of the mask layout. SLAVE has been successfully adapted to both bipolar and CMOS technologies; it provides error detection down to specific signal nets and device nodes and is extremely fast. SLAVE typically runs under 70 min on a VAX 11/780 for a complex IC containing up to 50K discrete devices and is modeled using six levels of hierarchical nesting.Keywords
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