Placement by Simulated Annealing on a Multiprocessor
- 1 July 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 6 (4), 534-549
- https://doi.org/10.1109/tcad.1987.1270301
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- Simulated Annealing Without Rejected MovesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- Convergence and finite-time behavior of simulated annealingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- The TimberWolf placement and routing packageIEEE Journal of Solid-State Circuits, 1985
- Hardware acceleration of gate array layoutPublished by Association for Computing Machinery (ACM) ,1985
- Global Wiring by Simulated AnnealingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983
- Optimization by Simulated AnnealingScience, 1983
- A Parallel Processing Approach for Logic Module PlacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983
- A Placement Algorithm for Array ProcessorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- A Module Interchange Placement MachinePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983