Orientation effect reduction through capless annealing of self-aligned planar GaAs Schottky barrier field-effect transistors
- 1 November 1983
- journal article
- Published by AIP Publishing in Applied Physics Letters
- Vol. 43 (9), 865-867
- https://doi.org/10.1063/1.94531
Abstract
A reduction in the orientation effect on self-aligned ion-implanted planar GaAs Schottky barrier field-effect transistors (FET’s) has been found. The FET’s were fabricated using capless annealing to avoid thermal stress that occurs at a dielectric/GaAs interface during capped annealing. Both mean and standard deviation in FET threshold voltage as a function of gate length are compared for FET’s oriented in the two perpendicular [110] directions. Very little orientation dependence is observed. Similar high-speed switching operation is also found for either orientation. These results indicate that stress-enhanced preferential lateral diffusion which appears to be a major factor in the orientation effect can be reduced through capless annealing.Keywords
This publication has 6 references indexed in Scilit:
- High-speed logic at 300K with self-aligned submicrometer-gate GaAs MESFET'sIEEE Electron Device Letters, 1983
- Self-aligned submicron gate digital GaAs integrated circuitsIEEE Electron Device Letters, 1983
- Orientation effect of self-aligned source/drain planar GaAs Schottky barrier field-effect transistorsApplied Physics Letters, 1983
- Capped versus capless heat treatment of molecular beam epitaxial GaAsApplied Physics Letters, 1982
- Proximate capless annealing of GaAs using a controlled-excess As vapor pressure sourceApplied Physics Letters, 1981
- Orientation effect on planar GaAs Schottky barrier field effect transistorsApplied Physics Letters, 1980