A 1 V 46 ns 16 Mb SOI-DRAM with body control technique

Abstract

Low-voltage and low-power DRAMs of appropriate capacity are required for portable systems such as portable PCs and Personal Digital Assistants (PDAs). Though a 1.2 V 49 ns bulk-DRAM has been reported, still lower voltage operation is difficult for bulk-DRAMs, due to the back bias effect and large junction capacitance. SOI devices have several advantages over bulk devices, such as small subthreshold swing (S-factor), elimination of the back bias effect, and small junction capacitance. To utilize these advantages, many SOI-DRAM studies and proposals have been made. The basic operation of the SOI-DRAM at 2.3 V has been examined using an experimental 64 kb SOI-DRAM, and a 3 V 50 ns 16 Mb SOI-DRAM has been also reported. Here the authors present a 1 V 46 ns 16 Mb SOI-DRAM which uses a 0.5 /spl mu/m CMOS/SIMOX process. To accelerate low-voltage speed, a body-pulsed sense amplifier (BPS) and body-driven equalizer (BDEQ) are used. The conventional body-control technique uses partially-depleted (PD) transistors. In contrast, fully-depleted (FD) transistors are used to reduce leakage current in the off-state.