Circuit optimization: Gate level modelling and multiobjective programming
- 31 January 1989
- journal article
- Published by Elsevier in Microprocessing and Microprogramming
- Vol. 25 (1-5), 171-176
- https://doi.org/10.1016/0165-6074(89)90191-9
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- Optimization-based transistor sizingIEEE Journal of Solid-State Circuits, 1988
- CMOS Circuit Speed and Buffer OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Macromodeling and Optimization of Digital MOS VLSI CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- A Switch-Level Timing Verifier for Digital MOS VLSIIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- An algorithm for CMOS timing and area optimizationIEEE Journal of Solid-State Circuits, 1984