Modeling the water related trap state created in pentacene transistors

Abstract

The authors report on the modeling of the water related trap state in pentacene single crystalfield-effect transistors that is created by a prolonged application of a gate voltage [C. Goldmann et al., Appl. Phys. Lett.88, 063501 (2006)]. The authors find a trap state narrow in energy to be appropriate to explain the steplike feature measured in the subthreshold region of the transfer characteristic. The trap state forms in an interface layer next to the gate insulator and is centered at 430 ± 50 meV above the valence band edge. The density increases from ( 2 to 10.5 ) × 10 18 ∕ cm 3 during gate bias stress. The knowledge of the details of this defect state can help to identify the physical and chemical origin of the created trap state.