Dislocations in thermally stressed silicon wafers

Abstract

To the author's knowledge, this is the first letter on the dislocation structures generated in silicon wafers by thermal stresses. These dislocations were caused by cooling in a room‐temperature ambient on removal from a furnace. The 〈110〉 60° type was dominant, although 〈112〉 dislocations were also observed. Their most important feature is that they tend to seek the shortest allowable paths in passing through the wafer thicknesswise. They often form fairly regular arrays in single or closely neighboring {111} planes, thus producing ensembles of etch pits (or mounds) that macroscopically resemble slip lines. The dislocation densities were often ∼10⁴ cm⁻²; these values agreed within an order of magnitude with those predicted by a simple stress relief mechanism.