FFT scaling in Domino CMOS gates
- 1 October 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 20 (5), 1067-1071
- https://doi.org/10.1109/jssc.1985.1052438
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- NORA: a racefree dynamic CMOS technique for pipelined logic structuresIEEE Journal of Solid-State Circuits, 1983
- High-speed compact circuits with CMOSIEEE Journal of Solid-State Circuits, 1982
- A dense gate matrix layout style for MOS LSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1980
- A CMOS microprocessor for telecommunications applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1977