An Evaluation of Several Two-Summand Binary Adders
- 1 June 1960
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IRE Transactions on Electronic Computers
- Vol. EC-9 (2), 213-226
- https://doi.org/10.1109/tec.1960.5219821
Abstract
Five fairly representative members of the class of two-summand binary adders are described and evaluated. Hopefully, this will help the development of more general approaches to computer subsystems evaluation. The adders are evaluated on the basis of three quantities: the number of two-input AND gates and OR gates, G; the gate-normalized addition time, τ; and the number of bits, n, in each summand. Three plausible formulas for computational efficiency, η, are postulated, and plotted vs n for the five adders. Based on a comparison of the resulting curves, the following efficiency formula seems preferable: η = n/τlog 2 G. Of the five adders considered, the new ``conditional-sum adder'' is best by the above formula when n≥ 3. Other adders, however, are shown to be superior when the assumptions underlying the evaluation of G and τ are changed. The evaluation is found to have several limitations; these are discussed. Curves of G and τ vs n are given. It is suggested that these curves can serve as raw data for other evaluations, so that various evaluation methods may be compared.Keywords
This publication has 5 references indexed in Scilit:
- Conditional-Sum Addition LogicIEEE Transactions on Electronic Computers, 1960
- The Residue Number SystemIEEE Transactions on Electronic Computers, 1959
- A One-Microsecond Adder Using One-Megacycle CircuitryIEEE Transactions on Electronic Computers, 1956
- Complexity in Electronic Switching CircuitsIRE Transactions on Electronic Computers, 1956
- Fast Carry Logic for Digital ComputersIEEE Transactions on Electronic Computers, 1955