High Speed Decimal Addition
- 1 August 1971
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-20 (8), 862-866
- https://doi.org/10.1109/t-c.1971.223362
Abstract
Parallel decimal arithmetic capability is becoming increasingly attractive with new applications of computers in a multi-programming environment. The direct production of decimal sums offers a significant improvement in addition over methods requiring decimal correction. These techniques are illustrated in the eight-digit adder which appears in the System/360 Model 195.Keywords
This publication has 2 references indexed in Scilit:
- High-Speed Arithmetic in Binary ComputersProceedings of the IRE, 1961
- A One-Microsecond Adder Using One-Megacycle CircuitryIEEE Transactions on Electronic Computers, 1956