Fabrication and testing investigation of low-voltage integrated electrophoresis chip based on silicon-on-insulator-MEMS

Abstract

A new approach has been developed to fabricate a low-voltage integrated electrophoresis chip based on silicon-on-insulator micro electron mechanical systems (SOI-MEMS). Arrayed-electrodes are embedded along the microchannel sidewall in the designed microchip. Because voltage should be applied effectively to arrayed-electrodes to serve as the driving force for the on-microchip electrophoresis, electrical isolation between arrayed-electrodes is essential for a practicable low-voltage integrated electrophoresis chip. Fabrication of arrayed-electrodes becomes the critical technique that governs the performance of the low-voltage integrated electrophoresis chip. Combined with the SOI substrate, full dielectric isolation is proposed to obtain high-performance integrated three-dimensional (3-D) sidewall arrayed-electrodes. The fabrication processes mainly consist of SOI wafer fabrication, narrow trench etching, polysilicon refilling and planarization, boron diffusion to form arrayed-electrodes, elicitation and protection of arrayed-electrodes, dry etching to obtain reservoirs and microchannels, etc. In order to obtain high-quality electrical isolation between arrayed-electrodes, process experiments were conducted to obtain optimized operational parameters. Poly (dimethylsiloxane) (PDMS) was selected as a cover to achieve a hybrid electrophoresis chip. The validity of the hybrid electrophoresis chip was tested by amino acid separation. Results showed high performance of the fabricated low-voltage integrated electrophoresis chip based on SOI-MEMS.