Architectural considerations involved in the design of an optical digital computer

Abstract

Communication problems such as interconnection bandwidth, clock skew, and connectivity restrict computational throughput. Bandwidth and clock skew problems limit the speed and add to the design complexity. Constrained connectivity forces a significant portion of the speed of a processor to be used to compensate for the limited number of interconnections. Philosophically, the large bandwidth, innate parallelism, and noninterfering propagation of optics offer mechanisms for overcoming these communication problems. The difficulty in exploiting these capabilities has been the absence of suitable optical logic and memory devices. Technologically, optical bistability and other advances in electrooptics now offer the possibility of cascadable optical logic elements with speed and power dissipation comparable with electronics. Architecturally, a parallel pipelined structure can be used to simplify the optical memory requirements as well as exploit the communication capabilities of optics.