Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation
- 1 March 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 9 (3), 236-247
- https://doi.org/10.1109/43.46799
Abstract
No abstract availableKeywords
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