A stochastic neural architecture that exploits dynamically reconfigurable FPGAs
- 30 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 202-211
- https://doi.org/10.1109/fpga.1993.279462
Abstract
In this paper we present an expandable digital architecturethat provides an efficient real time implementationplatform for large neural networks. The architecturemakes heavy use of the techniques of bit serialstochastic computing to carry out the large number ofrequired parallel synaptic calculations. In this designall real valued quantities are encoded on to stochasticbit streams in which the `1" density is proportionalto the given quantity. The actual digital circuitry issimple and...Keywords
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