A 160 MHz 32 b 0.5 W CMOS RISC microprocessor

Abstract

This custom VLSI implementation of a microprocessor architecture delivers 184 Drystone/MIPS at 162 MHz dissipating 0.5 W using an 1.5 V internal supply. The chip may also be operated at 215 MHz with a 2.0 V internal supply dissipating 1.1 W. The external interface always runs at 3.3 V. The die contains 2.1 M transistors and measures 7.8/spl times/6.4 mm/sup 2/. It is fabricated in 2.0 V 0.35 /spl mu/m 3-layer metal CMOS and packaged in a 144-pin thin quad flat pack. Clock generation uses an on-chip PLL with 3.68 MHz input clock to minimize high frequency clock signals on the board. The chip is pseudo-static and the internal clocks may be stopped in either phase to minimize power consumption.