A 320 MHz, 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generation

Publisher Website

23 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/isscc.1996.488540

Abstract

No abstract available

Keywords

This publication has 1 reference indexed in Scilit:

A PLL clock generator with 5 to 110 MHz of lock range for microprocessors
IEEE Journal of Solid-State Circuits, 1992

Cited by 16 articles