Path Delay Analysis for Hierarchical Building Block Layout System
- 1 January 1983
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 0738100X,p. 403-410
- https://doi.org/10.1109/dac.1983.1585684
Abstract
This paper describes a path delay analysis system which employs an accurate signal delay calculation method for MOS LSIs, taking poly resistance into account. The system takes mask patterns generated by a hierarchical building block layout system as inputs, and verifies timing margins of a large scale random logic LSI in a module-wise bottom up fashion. Path delay analysis using a critical path trace algorithm and an enumerative path trace algorithm in combination is effective in locating critical timing regions in a chip and in analyzing critical paths in the regions in detail.Keywords
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