A 280-ps Josephson 4-bitx4-bit parallel multiplier

Abstract

The multiplier circuit is implement in 5-/spl mu/m Resistor Coupled Josephson Logic (RCJL) and uses dual-rail logic aiming for high-speed operation. The array configuration was adopted for its design simplicity. The circuit contains 249 gates consisting of 862 Josephson junctions. The experimental multiplier was fabricated using 5-/spl mu/m lead-alloy Josephson IC processes. The complete operation of the multiplier was confirmed to be proper, with a critical path delay of 280 ps. The total power dissipation was 1 mW. This critical path delay is one order of magnitude, and the power dissipation more than two orders of magnitude smaller than those achieved with high-speed semiconductor devices, such as GaAs field-effect transistors and silicon bipolar transistors.