A variable-stress shallow trench isolation (STL) technology with diffused sidewall doping for submicron CMOS
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 92-95
- https://doi.org/10.1109/iedm.1988.32759
Abstract
A shallow trench isolation (STI) technology, RIE (reactive ion etching), CVD (chemical vapor deposition) oxide fill, and polarization are used to realize lithography-limited, submicron device and isolation dimensions. A novel boron diffusion technique is used for nMOSFET field doping, so that the parasitic sidewall inversion (leakage) problem is eliminated. It is shown that both the channel width bias and the narrow channel effect are greatly reduced in the STI technology. The diffused field also allows the boron doping to be self-aligned to the n-well with a single masking step in CMOS. STI is used in conjunction with a MINT (merged isolation and node trench) cell in 16-Mb DRAM (dynamic random access memory) technology.Keywords
This publication has 4 references indexed in Scilit:
- A practical trench isolation technology with a novel planarization processPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- Scaling limitations of submicron local oxidation technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- A simplified box (buried-oxide) isolation technology for megabit dynamic memoriesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- Deep trench isolated CMOS devicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982