High-density chain ferroelectric random access memory (chain FRAM)
- 1 May 1998
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 33 (5), 787-792
- https://doi.org/10.1109/4.668994
Abstract
No abstract availableThis publication has 12 references indexed in Scilit:
- A Staggered Nand Dram Array Architecture For A Gbit Scale IntegrationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A 4Mb DRAM with cross point trench transistor cellPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A 7.03-μm/sup 2/ Vcc/2-plate nonvolatile DRAM cell with a Pt/PZT/Pt/TiN capacitor patterned by one-mask dry etchingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 256 kb nonvolatile ferroelectric memory at 3 V and 100 nsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A half-micron ferroelectric memory cell technology with stacked capacitor structurePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A single-transistor ferroelectric memory cellPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- 2-V/100-ns 1T/1C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and nonrelaxation reference cellIEEE Journal of Solid-State Circuits, 1997
- High-density chain ferroelectric random-access memory (CFRAM)Published by Institute of Electrical and Electronics Engineers (IEEE) ,1997
- Ferroelectric Nonvolatile Memory Technology and Its ApplicationsJapanese Journal of Applied Physics, 1996
- An experimental DRAM with a NAND-structured cellIEEE Journal of Solid-State Circuits, 1993