Identification of Symmetry, Redundancy and Equivalence of Boolean Functions
- 1 December 1967
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electronic Computers
- Vol. EC-16 (6), 804-817
- https://doi.org/10.1109/pgec.1967.264726
Abstract
Functionally packaged logic can only be effectively utilized if the totality of switching functions that each package is capable of providing is recognized. Theorems concerning, and algorithms operating on, multiple output switching functions (possibly with don't care conditions) in cubical array notation are presented that 1) detect partial symmetry and redundancy sets of input varibles, 2) determine the function generated by a package with some of its inputs tied to logical 1 or 0 or tied together, and 3) rapidly show equivalence between two functions using symmetry information. While manual execution of the algorithms is possible, they are computer oriented. Results from actual computer experimentation show their efficiency.Keywords
This publication has 8 references indexed in Scilit:
- An Algorithm for Synthesis of Multiple-Output Combinational LogicIEEE Transactions on Computers, 1968
- Aids for Logic Design Algorithm DevelopmentIEEE Transactions on Education, 1967
- Solid Logic Design AutomationIBM Journal of Research and Development, 1964
- Detection of Total or Partial Symmetry of a Switching Function with the Use of Decomposition ChartsIEEE Transactions on Electronic Computers, 1963
- Minimization Over Boolean GraphsIBM Journal of Research and Development, 1962
- A computer program for the synthesis of combinational switching circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1961
- Algebraic Topological Methods for the Synthesis of Switching Systems. ITransactions of the American Mathematical Society, 1958
- The Problem of Simplifying Truth FunctionsThe American Mathematical Monthly, 1952