An Algorithm for Synthesis of Multiple-Output Combinational Logic
- 1 February 1968
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-17 (2), 117-128
- https://doi.org/10.1109/tc.1968.227399
Abstract
Abstract—A computer-oriented algorithm for synthesizing combinational logic circuits from a collection of functionally packaged circuits is developed. The algorithm uses a hierarchy of "goals" in an iterative decision process in a manner similar to that employed by theorem proving and gamne playing programs. With each iteration a set of "tasks" finds the circuit package which satisfies the highest level goal while meeting circuit constraints.Keywords
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