Logic verification algorithms and their parallel implementation
- 1 January 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 8 (2), 181-189
- https://doi.org/10.1109/43.21836
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- A logic verifier based on Boolean comparisonPublished by Association for Computing Machinery (ACM) ,1986
- Logic Minimization Algorithms for VLSI SynthesisPublished by Springer Nature ,1984
- An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic CircuitsIEEE Transactions on Computers, 1981
- Hardware VerificationIEEE Transactions on Computers, 1977