Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
- 1 March 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-36 (3), 344-355
- https://doi.org/10.1109/tc.1987.1676906
Abstract
The incorporation of different forms of redundancy has been recently proposed for various VLSI and WSI designs. These include regular architectures, built by interconnecting a large number of a few types of system elements on a single chip or wafer. The motivation for introducing fault-tolerance (redundancy) into these architectures is two-fold: yield enhancement and performance (like computational availability) improvement.Keywords
This publication has 15 references indexed in Scilit:
- Wafer-Scale Integration of Systolic ArraysIEEE Transactions on Computers, 1985
- Configuration of VLSI Arrays in the Presence of DefectsJournal of the ACM, 1984
- Characterizing the LSI Yield Equation from Wafer Test DataIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1984
- The Diogenes Approach to Testable Fault-Tolerant Arrays of ProcessorsIEEE Transactions on Computers, 1983
- Integrated circuit yield statisticsProceedings of the IEEE, 1983
- Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI DesignsIEEE Transactions on Computers, 1982
- Fault-tolerant wafer-scale architectures for VLSIACM SIGARCH Computer Architecture News, 1982
- Markov Models for Multiple Bus Multiprocessor SystemsIEEE Transactions on Computers, 1982
- Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good ProductIBM Journal of Research and Development, 1980
- Fault Coverage in Digital Integrated CircuitsBell System Technical Journal, 1978