The flexibility dedicated approach: reconfigurable arrays for low-level image processing

Abstract

Rather than considering a fully programmable SIMD (single-instruction-multiple-date-stream) solution, the authors present a flexibly dedicated approach, by which a number of relevant algorithms can be mapped onto a parallel architecture designed for real-time Fourier transform (FFT) processing, with a modest increase in complexity of the individual elements of the architecture itself. The authors have verified that: (1) at the architectural level, it is sufficient to introduce a suitable data feeder without needing to augment or otherwise modify the basic interconnection network; (2) with regard to the functions of the individual PE, the basic requirements for FFT operations are well capable of supporting the extended set of functions introduced by the low-level processing algorithms; and (3) with regard to the system control, by introducing a simple communication protocol no need for global signals arises, other than a basic reset signal. Thus, a much larger set of functions can be extracted from the base architecture with a moderate cost in terms of silicon requirements and speed decrease; other factors relevant in a design environment (typically, limitation of global signals) are also accounted for.