Design-performance trade-offs in CMOS-domino logic
- 1 April 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 21 (2), 304-306
- https://doi.org/10.1109/jssc.1986.1052519
Abstract
No abstract availableThis publication has 3 references indexed in Scilit:
- Differential split-level CMOS logic for sub-nanoseconds speedsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- Cascode voltage switch logic: A differential CMOS logic familyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- High-speed compact circuits with CMOSIEEE Journal of Solid-State Circuits, 1982