Lanthanum silicate gate dielectric stacks with subnanometer equivalent oxide thickness utilizing an interfacial silica consumption reaction

Abstract

A silicate reaction between lanthana and silica layers has been utilized to eliminate interfacial silica in metal-insulator-semiconductor devices and to obtain devices with very low equivalent oxide thickness (EOT). This provides a simple process route to interface elimination, while producing a silicate dielectric with a higher temperature stability of the amorphous phase. The ${\mathrm{La}}_2{\mathrm{O}}_3$ layers in this study are deposited by reactive evaporation on (001) Si covered by a $\sim 0.8–1.0\text{‐}\mathrm{nm}$ -thick ${\mathrm{SiO}}_2$ chemical oxide, and are capped in situ with a Ta gate, followed by a reaction anneal, which lowers the EOT from greater than 1.5 nm for the as-deposited bilayer stack to as low as 0.5 nm. Electron energy-loss spectroscopy and medium-energy ion scattering are used to show that a temperature of 400 °C is sufficient for the formation of the silicate gate dielectric. Gate leakage currents as low as $0.06\mathrm{A}∕{\mathrm{cm}}^2$ are obtained for stacks having an EOT of 0.63 nm, orders of magnitude below that of ${\mathrm{SiO}}_2$ having the same EOT value. Electrical breakdown is observed at applied fields above $16\mathrm{MV}∕\mathrm{cm}$ .