Differential split-level CMOS logic for subnanosecond speeds

Abstract

Subnanosecond gate delays (0.8 n) have been measured on complex logic gates (e.g., sum functions of a full adder) designed in the differential split-level (DSL) CMOS circuit technique. This fdgh speed has been achieved by reducing the logic swing (2.4 V) on interconnect lines between logic gates, by using current controlled caseoded cross-coupled NMOS-PMOS loads, by using combhsed open NMOS drains as outputs, and by employiug shorter channel lengths ( Leff= 1ym) for the NMOS devices in the logic trees with reduced maximum drain-source voltages to avoid reliability problems. Extra ion implantation protects these transistors from punchthrough. The DSL circuit technique was implemented in a dou- ble-metal 2.5-Vm CMOS n-well process with conventional 2.5-p,m projection lithography, except for the polysilicon. In this mask only the gate length of the n-channel tran- sistors in the logic trees is decreased to 1.5 pm (-Leff = 1 pm), while the other polysilicon details and pitches remain constant. Therefore a stepper exposure is used for the polysilicon definition. An extra deep boron implant pro- tects the short-channel NMOS transistors from punchthrough. DSL incorporates a reduced maximum drain-source voltage V~~~= in the logic trees resulting in less hot-elec- tron-induced degradation of these devices. Decreasing v~~~m reduces the lateral electric field near the drain edge of these NMOS transistors (3), (4). This allows the use of shorter channel lengths without lifetime reduction.