Direct-coupled FET logic circuits on InP
- 1 March 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 12 (3), 98-100
- https://doi.org/10.1109/55.75724
Abstract
A process technology for direct-coupled FET logic (DCFL) circuits on InP substrates, based on enhancement-mode InGaAs/InAlAs heterostructure-insulated-gate FETs (HIGFETs) is discussed. Its performance was demonstrated by fabricating 11- and 19-stage ring oscillators. The circuits were fabricated on undoped lattice-matched heterostructures grown by molecular beam epitaxy (MBE), using a refractory-gate process with self-aligned sidewalls to achieve a lightly-doped-drain (LDD) structure. For a gate length of 1.2 mu m, with V/sub dd/=2 V, the best propagation delay observed was 23 ps/stage, with associated power of 2.2 mW/stage.<>Keywords
This publication has 7 references indexed in Scilit:
- Selectively dry-etched n/sup +/-GaAs/N-InAlAs/InGaAs HEMTs for LSIIEEE Electron Device Letters, 1990
- High aspect ratio 0.1 μm tungsten gates for InGaAs/InAlAs heterojunction transistorsJournal of Vacuum Science & Technology B, 1989
- Impact of buffer layer design on the performance of AlInAs-GaInAs HEMTsIEEE Transactions on Electron Devices, 1989
- Threshold voltage of submicron Ga0.47In0.53As HIGFETsElectronics Letters, 1989
- Ultra-high-speed digital circuit performance in 0.2- mu m gate-length AlInAs/GaInAs HEMT technologyIEEE Electron Device Letters, 1988
- Current-gain cutoff frequency comparison of InGaAs HEMTsIEEE Electron Device Letters, 1988
- Velocity-field characteristics of Ga1−xInxP1−yAsy quaternary alloysApplied Physics Letters, 1977