Annealing kinetics in amorphous silicon field-effect transistors

Abstract

After intentional degradation of amorphous silicon-silicon nitride field-effect transistors by applying a positive gate bias stress and light illumination, their characteristics were studied during isochronal annealing. The dependence on the annealing temperature of the source-drain current as well as the threshold voltage provided evidence for multiple stages of annealing. A peak at around 160°C can be associated with annealing of bulk metastable defect states in the a-Si: H and one at about 110°C with annealing of interface defects. Annealing below about 80°C probably originates from charge trapping in the silicon nitride layer. From the hydrogen-diffusion model of the kinetics, a method of distinguishing the annealing of different kinds of defect states is proposed.