Annealing kinetics in amorphous silicon field-effect transistors
- 1 May 1992
- journal article
- research article
- Published by Taylor & Francis in Philosophical Magazine Part B
- Vol. 65 (5), 933-944
- https://doi.org/10.1080/13642819208217911
Abstract
After intentional degradation of amorphous silicon-silicon nitride field-effect transistors by applying a positive gate bias stress and light illumination, their characteristics were studied during isochronal annealing. The dependence on the annealing temperature of the source-drain current as well as the threshold voltage provided evidence for multiple stages of annealing. A peak at around 160°C can be associated with annealing of bulk metastable defect states in the a-Si: H and one at about 110°C with annealing of interface defects. Annealing below about 80°C probably originates from charge trapping in the silicon nitride layer. From the hydrogen-diffusion model of the kinetics, a method of distinguishing the annealing of different kinds of defect states is proposed.Keywords
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