About Random Fault Detection of Combinational Networks
- 1 June 1976
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-25 (6), 659-664
- https://doi.org/10.1109/tc.1976.1674669
Abstract
Fault detection by applying a random input sequence simultaneously to a network under test and to a reference network is conside-red. A distinction between testing quality and detection quality is given. The detection surface is introduced as a characteristic parameter of a combinational network. The results are applied to TTL combinational circuits.Keywords
This publication has 4 references indexed in Scilit:
- The Error Latency of a Fault in a Sequential Digital CircuitIEEE Transactions on Computers, 1976
- Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic NetworksIEEE Transactions on Computers, 1975
- Analysis of Logic Circuits with Faults Using Input Signal ProbabilitiesIEEE Transactions on Computers, 1975
- An Automatic Test Generation System for Illiac IV Logic BoardsIEEE Transactions on Computers, 1972