A high-speed 16-kbit n-MOS random-access memory
- 1 October 1976
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 11 (5), 585-590
- https://doi.org/10.1109/JSSC.1976.1050785
Abstract
This paper presents one version of a high-speed 16-kbit dynamic MOS random-access memory (RAM). This memory utilizes a one transistor cell with an area of 22/spl times/36 /spl mu/m/SUP 2/ which is fabricated using advanced n-channel silicon-gate MOS technology (5-/spl mu/m photolithography). The main feature of the design is a sense circuitry scheme, which allows a high speed (read access time of 200 ns) with low-power dissipation (600 mW at the 400-ns cycle time). The fully decoded memory is fabricated on a 5/spl times/7 mm/SUP 2/ chip and is assembled in a 22-lead ceramic dual-in-line package.Keywords
This publication has 3 references indexed in Scilit:
- Peripheral circuits for one-transistor cell MOS RAM'sIEEE Journal of Solid-State Circuits, 1975
- A 4096-bit high-speed emitter-coupled-logic (ECL) compatible random-access memoryIEEE Journal of Solid-State Circuits, 1975
- A 1-mil/SUP 2/ single-transistor memory cell in n silicon-gate technologyIEEE Journal of Solid-State Circuits, 1973