HAL; A Block Level Hardware Logic Simulator
- 1 January 1983
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 150-156
- https://doi.org/10.1109/dac.1983.1585641
Abstract
A special purpose hardware machine, which simulates up to one half million gates and 2M byte RAM ICs at a 5 millisecond clock speed, is described. This is accomplished with a HArdware Logic (HAL) simulator. This performance is achieved with 32 distributed special parallel processors, which utilize Block Oriented Simulation Technique. The technique promises a good cost hardware logic simulator.Keywords
This publication has 4 references indexed in Scilit:
- HAL: A High-Speed Logic Simulation MachineIEEE Design & Test of Computers, 1985
- The Yorktown Simulation Engine: IntroductionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- A Logic Simulation MachinePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- The Yorktown Simulation EnginePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982