A 3.8 ns CMOS 16×16 multiplier using complementary pass transistor logic

Publisher Website

1 January 1989

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/cicc.1989.56843

Abstract

No abstract available

This publication has 1 reference indexed in Scilit:

A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic
IEEE Journal of Solid-State Circuits, 1987

Cited by 7 articles