A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic
- 1 August 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 22 (4), 528-532
- https://doi.org/10.1109/jssc.1987.1052767
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- Design procedures for differential cascode voltage switch circuitsIEEE Journal of Solid-State Circuits, 1986
- Accurate simulation of power dissipation in VLSI circuitsIEEE Journal of Solid-State Circuits, 1986
- Differential split-level CMOS logic for sub-nanoseconds speedsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- Cascode voltage switch logic: A differential CMOS logic familyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- NORA: a racefree dynamic CMOS technique for pipelined logic structuresIEEE Journal of Solid-State Circuits, 1983
- High-speed compact circuits with CMOSIEEE Journal of Solid-State Circuits, 1982