A 1.5 ns 32 b CMOS ALU in double pass-transistor logic
- 1 January 1993
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A 32-b CMOS ALU (arithmetic and logic unit), fabricated using 0.25- mu m CMOS technology, that has a 1.5-ns addition time with a 2.5-V supply, is described. This addition time is achieved using double pass-transistor logic (DPL) and a conditional carry-selection (CCS) carry look-ahead circuit. The measured supply-voltage dependence of ALU addition time is shown, revealing excellent low-voltage performance. DPL AND/NAND and OR/NOR ring oscillators show measured speed improvements of 15% and 30% over CMOS NAND and NOR ring oscillators.<>Keywords
This publication has 2 references indexed in Scilit:
- A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logicIEEE Journal of Solid-State Circuits, 1990
- Realization of transmission-gate conditional-sum (TGCS) adders with low latency timeIEEE Journal of Solid-State Circuits, 1989