Realization of transmission-gate conditional-sum (TGCS) adders with low latency time
- 1 June 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 24 (3), 558-561
- https://doi.org/10.1109/4.32007
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
- Realization of a DPCM coder for 13.5-MHz sampling rate in CMOS technologyIEEE Journal of Solid-State Circuits, 1987
- A high-speed multiplier using a redundant binary adder treeIEEE Journal of Solid-State Circuits, 1987
- A Pipelined 330-MHz MultiplierIEEE Journal of Solid-State Circuits, 1986
- A CMOS floating point multiplierIEEE Journal of Solid-State Circuits, 1984
- A Regular Layout for Parallel AddersIEEE Transactions on Computers, 1982
- On the Time Required to Perform AdditionJournal of the ACM, 1965
- An Evaluation of Several Two-Summand Binary AddersIRE Transactions on Electronic Computers, 1960
- Conditional-Sum Addition LogicIEEE Transactions on Electronic Computers, 1960